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  rev.2.00 sep 14, 2006 page 1 of 10 M62490FP electric volume control with tone controller for 4-speaker applications rej03f0213-0200 rev.2.00 sep 14, 2006 description ? developed for car audio ? uses it for analog small signal handling of stage before power amplifier ? use to home audio system, television are thought about other than car audio system features ? built-in zero cross detector prevents click noise ? differential amplifier ? loudness ? tone control bass/mid/treble ? master volume/f ader volume ? serial data control recommended operating conditions supply voltage range: v cc = 6 to 9 v v dd = 4 to 6 v rated supply voltage: v cc = 8 v v dd = 5 v block diagram defn in2 defn in1 defp in1 defp in2 lchin rchin differential amplifier differential amplifier mixing amp mixing amp volume & loudness bass/ mid/ treble bass/ mid/ treble zero cross detector zero cross detector -com interfase fader fader lch rch front front rear rear
M62490FP rev.2.00 sep 14, 2006 page 2 of 10 pin configuration and application example 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 rd cd tape tv vcr v cc + ? 2.2 10 k 820 p 1.6 k 0.22 0.068 0.068 6.8 k 0.01 1 rrout frout v dd n.c. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 vcr tv tape cd rd 47 k + ? 2.2 10 k 820 p 1.6 k 0.22 0.068 0.068 6.8 k 0.01 1 rrout frout 10 47 k outside harmonic parts for mid outside harmonic parts mid loudness on loudness off off on on off sw a sw b 0.22 mcu v cc (analog) differential amplifier sw 56 k 22 k 22 k 56 k a b loudness sw + ? + ? + ? + ? + ? + ? zero cross detector + ? + ? v dd (digital) ref differential amplifier sw 56 k 22 k 22 k 56 k a b loudness sw + ? + ? + ? + ? + ? + ? zero cross detector + ? + ? v cc i/f timer detector gnd 200 k + ?
M62490FP rev.2.00 sep 14, 2006 page 3 of 10 pin description pin no. symbol function 1 ref ic signal ground. apply 1/2 v cc 2 defp in1 differential amplifier input + 3 defn in1 differential amplifier input ? 4 mix in1 mixing amplifier input ? 5 mix out1 mixing amplifier input + 6 vol in1 input pin of the volume block 7 loud in1 pin for setting the frequency characteristics of the loudness block 8 bassa1 9 bassb1 pin for setting the frequency characteristics of the tone (bass) block 10 mid1 r-ladder terminal of tone (mid) 11 tre1 r-ladder terminal of tone (treble) 12 tone out1 output pin of the tone block 13 fader in1 input pin of the fader volume 14 rear out1 output pin of the fader volume (rear) 15 front out1 output pin of the fader volume (front) 16 gnd ground 17 tim1 timer setting terminal the relationship between outside parts c and setting time is t = 13.8 10 4 ? c (s). 18 data input pin of the control data this pin inputs data in synchronization with clock 19 clock clock input pin for serial data transfer 20 n.c. non connection 21 v dd digital power supply pin, normally +5 v 22 front out2 output pin of the fader volume (front) 23 rear out2 output pin of the fader volume (rear) 24 fader in2 input pin of the fader volume 25 tone out2 output pin of the tone block 26 tre2 r-ladder terminal of tone (treble) 27 mid2 r-ladder terminal of tone (mid) 28 bassb2 29 bassa2 pin for setting the frequency characteristics of the tone (bass) block 30 loud in2 pin for setting the frequency characteristics of the loudness block 31 vol in2 input pin of the volume block 32 mix out2 mixing amplifier output 33 mix in2 mixing amplifier input 34 defn in2 differential amplifier input ? 35 defp in2 differential amplifier input + 36 v cc analog power supply pin
M62490FP rev.2.00 sep 14, 2006 page 4 of 10 absolute maximum ratings item symbol ratings unit conditions supply voltage v cc , v dd 10, 7 v power dissipation pd 990 mw ta 25 c thermal derating ratio k 9.9 mw/ c ta 25 c operating temperature topr ?30 to 85 c storage temperature tstg ?55 to 125 c 25 50 75 100 125 150 85 385 960 1000 800 600 400 200 thermal derating power dissipation pd (mw) ambient temperature ta ( c)
M62490FP rev.2.00 sep 14, 2006 page 5 of 10 electrical characteristics ta = 25 c, v cc = 8 v, v dd = 5 v, vol/fader = 0 db, tone/flat, loudness off unless otherwise noted limits item symbol min typ max unit test conditions circuit current i cc ? 20 35 ma no input signal pass gain gv ?3.5 0 3.5 db outside resister 22 k ? of pin 4, 33 outside resister 56 k ? of pin 2, 3, 34, 35 maximum attenuation a tt (vol) ?32.5 ?30 ?27.5 db vi = 1 vrms, f = 1 khz att (vol) = ?30 db attenuation error ? a tt (vol) ?2.5 0 2.5 db att (vol) = 0 db maximum input voltage v im 1.8 2.2 ? vrms f = 1 khz, bw: 400 hz to 30 khz thd = 1% bass boost g (bass) b 13 16 19 db f = 100 hz bass cut g (bass) c ?15 ?12 ?9 db f = 100 hz mid boost g (mid) b 9 12 15 db f = 1 khz (outside harmonic amplifier) mid cut g (mid) c ?15 ?12 ?9 db f = 1 khz (outside harmonic amplifier) treble boost g (tre) b 9 12 15 db f = 10 khz treble cut g (tre) c ?15 ?12 ?9 db f = 10 khz maximum attenuation a tt (fed) ? ?90 ?80 db vi = 1 vrms, f = 1 khz att (fed) = ? db maximum output voltage v om 1.8 2.2 ? vrms f = 1 khz, bw: 400 hz to 30 khz thd = 1% v no 1 ? 10 18 rg = 0, din-audio output noise voltage v no 2 ? 3 8 vrms att (vol) = ?30 db att (fed) = ? db rg = 0, din-audio total harmonic distortion thd ? 0.03 0.05 % f = 1 khz, vo = 0.5 vrms bw: 400 hz to 30 khz channel separation cs ? ?90 ?80 db f = 1 khz cross talk of differential amplifier sw ct ? ?75 ?65 db f = 1 khz g (loud) l 7.0 11.0 15.0 loudness on f = 100 hz, att (vol) = ?30 db voltage gain of loudness g (loud) h 3.5 6.5 9.5 db loudness on f = 10 khz, att (vol) = ?30 db
M62490FP rev.2.00 sep 14, 2006 page 6 of 10 relationship between data and clock clock data d0 d1 d2 d3 d12 d15 d16 data reading mode; the rising edge of the clock signal latch reading mode; the falling edge of the clock signal latch signal "h" digital circuit dc characteristics limits item symbol min typ max unit test conditions "l" level input voltage v il 0 ~ 0.2 v dd "h" level input voltage v ih 0.8 v dd ~ v dd v data, clock pins "l" level input current i il ?10 ? 10 v i = 0 "h" level input current i ih ? ? 10 a v i = v dd data, clock pins digital circuit ac characteristics limits item symbol min typ max unit clock cycle time t cr 4 ? ? clock pulse width ("h" level) t whc 1.6 ? ? clock pulse width ("l" level) t wlc 1.6 ? ? clock rise time t r ? ? 0.4 clock fall time t f ? ? 0.4 data setup time t sd 0.8 ? ? data hold time t hd 0.8 ? ? s
M62490FP rev.2.00 sep 14, 2006 page 7 of 10 clock data timing clock data 75% 25% t r t f t whc t wlc t sd t hd t cr
M62490FP rev.2.00 sep 14, 2006 page 8 of 10 data input format 0: differential amplifier sw off 1: differential amplifier sw on 0: loudness off 1: loudness on 0: 1ch 1: 2ch 0: both channel 1: side channel data select (d15,d16) 00: volume/differential amplifier sw/loudness 10: fader 01: bass/treble/mid 0: front point zero detect 1: rear point zero detect d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 d16 0/1 0/1 0/1 0/1 0/1 0 fader (rear) (attf1) fader (front) (attf2) volume ch1 (attv1) volume ch1 (attv2) volume ch2 (attv1) volume ch2 (attv2) fader (front) (attf1) bass treble mid 0 0 fader (rear) (attf2) 0 0 1 0 0 0 1 volume code ch1 d2 d3 d4 ch1 d5 d6 attv1 ch2 d7 d8 d9 attv2 ch2 d10 d11 0 db 1 0 1 0 db 1 1 ?4 db 0 0 1 ?1 db 0 1 ?8 db 1 1 0 ?2 db 1 0 ?12 db 0 1 0 ?3 db 0 0 ?16 db 1 0 0 ?20 db 0 0 0 ?24 db 0 1 1 ?28 db 1 1 1 fader code front d2 d3 d4 d5 front d6 d7 attf1 rear d8 d9 d10 d11 attf2 rear d12 d13 0 db 1 0 0 1 0 db 1 1 ?2 db 0 0 0 1 ?2 db 0 1 ?4 db 0 1 0 1 ?4 db 1 0 ?6 db 1 1 0 1 ?6 db 0 0 ?8 db 1 1 1 0 ?10 db 0 0 1 1 (please keep attf2 to 0 db when you set fader code from 0 db to ?16 db) ?12 db 1 0 1 1 ?14 db 0 1 1 1 ?16 db 0 1 1 0 ?24 db 1 0 1 0 ?32 db 0 0 1 0 ?40 db 1 1 0 0 ?48 db 0 1 0 0 ?56 db 1 0 0 0 ? db 0 0 0 0
M62490FP rev.2.00 sep 14, 2006 page 9 of 10 tone code bass d0 d1 d2 d3 16 db 0 0 0 1 14 db 1 1 1 0 12 db 0 1 1 0 10 db 1 0 1 0 8 db 0 0 1 0 6 db 1 1 0 0 4 db 0 1 0 0 2 db 1 0 0 0 0 db 0 0 0 0 ?2 db 1 0 0 1 ?4 db 0 1 0 1 ?6 db 1 1 0 1 ?8 db 0 0 1 1 ?10 db 1 0 1 1 ?12 db 0 1 1 1 treble d4 d5 d6 d7 12 db 0 1 1 0 10 db 1 0 1 0 8 db 0 0 1 0 6 db 1 1 0 0 4 db 0 1 0 0 2 db 1 0 0 0 0 db 0 0 0 0 ?2 db 1 0 0 1 ?4 db 0 1 0 1 ?6 db 1 1 0 1 ?8 db 0 0 1 1 ?10 db 1 0 1 1 ?12 db 0 1 1 1 mid d8 d9 d10 d11 12 db 0 1 1 0 10 db 1 0 1 0 8 db 0 0 1 0 6 db 1 1 0 0 4 db 0 1 0 0 2 db 1 0 0 0 0 db 0 0 0 0 ?2 db 1 0 0 1 ?4 db 0 1 0 1 ?6 db 1 1 0 1 ?8 db 0 0 1 1 ?10 db 1 0 1 1 ?12 db 0 1 1 1
M62490FP rev.2.00 sep 14, 2006 page 10 of 10 package dimensions y index mark 1 18 19 36 f *1 *2 *3 e h e d e b p a c detail f a 2 l a 1 include trim offset. dimension "*3" does not note) do not include mold flash. dimensions "*1" and "*2" 1. 2. previous code jeita package code renesas code prsp0036ga-a 36p2r-a mass[typ.] 0.5g p-ssop36-8.4x15-0.80 0.2 0.15 0.13 0.5 0.4 0.35 max nom min dimension in millimeters symbol reference 15.2 15.0 14.8 d 8.6 8.4 8.2 e 2.0 a 2 12.23 11.93 11.63 2.4 a 0.05 0.7 0.5 0.3 l 10 0 c 0.8 e 0.15 y h e a 1 b p 0.65 0.95
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies o r errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas techn ology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technology corp. is necessary to reprint or reproduce in whole or in part these materi als. 7. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a lic ense from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. 8. please contact renesas technology corp. for further details on these materials or the products contained therein. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 200 6. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .6.0


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